Understanding Program/Erase (P/E) Cycles
In NAND architecture, data can be read and written at the page level (typically 4KB to 16KB), but cannot be overwritten until an entire block (consisting of 128 to 512 pages, roughly 2MB to 8MB) is erased. This fundamental physical constraint dictates that flash memory cells degrade with every erase cycle. Modern SSD controllers utilize dynamic wear-leveling algorithms to distribute write cycles evenly across all NAND blocks.